AM335X LCD Driver code

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[cpp]
/*
* Copyright (C) 2008-2009 MontaVista Software Inc.
* Copyright (C) 2008-2009 Texas Instruments Inc
*
* Based on the LCD driver for TI Avalanche processors written by
* Ajay Singh and Shalom Hai.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option)any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/fb.h>
#include <linux/dma-mapping.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/uaccess.h>
#include <linux/interrupt.h>
#include <linux/clk.h>
#include <linux/cpufreq.h>
#include <linux/console.h>
#include <linux/spinlock.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/pm_runtime.h>
#include <video/da8xx-fb.h>
#include <asm/mach-types.h>

#define DRIVER_NAME "da8xx_lcdc"

#define LCD_VERSION_1   1
#define LCD_VERSION_2   2

/* LCD Status Register */
#define LCD_END_OF_FRAME1       BIT(9)
#define LCD_END_OF_FRAME0       BIT(8)
#define LCD_PL_LOAD_DONE        BIT(6)
#define LCD_FIFO_UNDERFLOW      BIT(5)
#define LCD_SYNC_LOST           BIT(2)

/* LCD DMA Control Register */
#define LCD_DMA_BURST_SIZE(x)       ((x) << 4)
#define LCD_DMA_BURST_1         0x0
#define LCD_DMA_BURST_2         0x1
#define LCD_DMA_BURST_4         0x2
#define LCD_DMA_BURST_8         0x3
#define LCD_DMA_BURST_16        0x4
#define LCD_V1_END_OF_FRAME_INT_ENA BIT(2)
#define LCD_V2_END_OF_FRAME0_INT_ENA    BIT(8)
#define LCD_V2_END_OF_FRAME1_INT_ENA    BIT(9)
#define LCD_DUAL_FRAME_BUFFER_ENABLE    BIT(0)

/* LCD Control Register */
#define LCD_CLK_DIVISOR(x)      ((x) << 8)
#define LCD_RASTER_MODE         0x01

/* LCD Raster Control Register */
#define LCD_PALETTE_LOAD_MODE(x)    ((x) << 20)
#define PALETTE_AND_DATA        0x00
#define PALETTE_ONLY            0x01
#define DATA_ONLY           0x02

#define LCD_MONO_8BIT_MODE      BIT(9)
#define LCD_RASTER_ORDER        BIT(8)
#define LCD_TFT_MODE            BIT(7)
#define LCD_V1_UNDERFLOW_INT_ENA    BIT(6)
#define LCD_V2_UNDERFLOW_INT_ENA    BIT(5)
#define LCD_V1_PL_INT_ENA       BIT(4)
#define LCD_V2_PL_INT_ENA       BIT(6)
#define LCD_MONOCHROME_MODE     BIT(1)
#define LCD_RASTER_ENABLE       BIT(0)
#define LCD_TFT_ALT_ENABLE      BIT(23)
#define LCD_STN_565_ENABLE      BIT(24)
#define LCD_V2_DMA_CLK_EN       BIT(2)
#define LCD_V2_LIDD_CLK_EN      BIT(1)
#define LCD_V2_CORE_CLK_EN      BIT(0)
#define LCD_V2_LPP_B10          26
#define LCD_V2_TFT_24BPP_MODE       BIT(25)
#define LCD_V2_TFT_24BPP_UNPACK     BIT(26)

/* LCD Raster Timing 2 Register */
#define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16)
#define LCD_AC_BIAS_FREQUENCY(x)        ((x) << 8)
#define LCD_SYNC_CTRL               BIT(25)
#define LCD_SYNC_EDGE               BIT(24)
#define LCD_INVERT_PIXEL_CLOCK          BIT(22)
#define LCD_INVERT_LINE_CLOCK           BIT(21)
#define LCD_INVERT_FRAME_CLOCK          BIT(20)

/* LCD Block */
#define LCD_PID_REG                0x0
#define LCD_CTRL_REG               0x4
#define LCD_STAT_REG               0x8
#define LCD_RASTER_CTRL_REG            0x28
#define LCD_RASTER_TIMING_0_REG        0x2C
#define LCD_RASTER_TIMING_1_REG        0x30
#define LCD_RASTER_TIMING_2_REG        0x34
#define LCD_DMA_CTRL_REG           0x40
#define LCD_DMA_FRM_BUF_BASE_ADDR_0_REG    0x44
#define LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG 0x48
#define LCD_DMA_FRM_BUF_BA

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